Verilog RTL Softcore Of 65816 (Electronic, Engineering, Other (Engineering), Testing / Quality Assurance)

Verilog RTL Softcore Of 65816

Job Summary:

Job Type:	Project
Budget:	$ 100-250
Required Skills:	Electronic, Engineering, Other (Engineering), Testing / Quality Assurance
Attached Files:	(None)

Status:	Closed for bidding

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1 reviews

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2 posted 1 paid

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Hong Kong, Hong Kong

Member Since:

July 27, 2006

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Description

Need a RTL soft core of 65816 MCU in verilog.

1/ The deliverable must be as a verilog top module and sub-modules of same signal names as in the datasheet.

2/ The design should be error free, contain all source code in verilog only and not using any proprietary libraries, only default verilog libraries are allow.
It should synthesize-able and complete with a test bench containing test vectors to exercise all the instruction set, register flags testing and each addressing modes must be exercised at least once.

3/ Design should be completely synchronous in design using only one edge of the clock.

4/ Design should include detail documentation within the source codes to provide easy mantainence and bug tracing.

5/ The execution clock count per instruction should be the same as in the datasheet.

For details, one example of the datasheet of 65816 can be found here
http://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf

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