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Rating: (No Feedback Yet)
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NDA-Bitlaw-20080606.pdf
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Description
This project calls to program an FPGA based solution. Coder/seller to provide FPGA code to make an SCSI to SATA adapter. SCSI refer to all SCSI types – e.g.: SCSI1,2,3 & SCSI320. Coder/seller (designer) may use SCSI and SATA2 cores and allowed to implement and embedded (soft or hard coded) PPC/other CPU into the FPGA. Coder/seller to suggest the best (also in terms of cost) FPGA device to match this project. SCSI interface is seen as device (to the "world") and SATA2 interface side is to behave as "Host" (so it would control an external SATA device). All data read/write/DMA and control functions of both buses must be fully supported. Full self diagnostics must be included at this project scope. A minimum (for both buses) date rate speed is required by bus's specifications. This is an embedded application and coder will be granted the full specifications, board general architecture & parameters after signing the NDA. We will let the coder, after verifying his application solution concept, solution block diagram, basic state machine description and theoretical prove to write the FPGA code. We may optionally provide cores purchasing. H/W schematic design is optional and would be later discussed upon Coder/seller expertise. Coder/seller would supply a working solution based on "of the shelf" FPGA board with tailored harness & extra electronics.
Additional information:
Submitted on 06/09/2008 at 12:21 EDT
NDA to be signed.
Reminder
You may not start working in this and any project before
your bid is accepted. Any user who violates this policy
may have their account permanently suspended.
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Melbourne,
AU
location |
US$3,200
bid amount |

         
(1
reviews)
feedback |

35 day(s)
delivery time |

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Intelligence Software Company ( ITSOFTCO)
We are confident to provide clients with:
+ Software products and solutions with high quality, competitive price and schedule guaranty
+ Optimal designs and solutions for a professional and impressive e- commerce website
Perfect customer support service
+ All products and services developed by ISOFTCO are attached with special importance on offering added values to customers, updating innovative technology and ensuring international standards
Client-Server: Java/Java Technology, C#/.NET Technologies, VB 6.0 ComponentOne, Utilities
Portal/CMS: JSP/JSF/Servlet/EJB Technology, Java/Java Technology, Jakarta Strust Technology, Jakarta Log4J, Hibernate, Spring Framework, XML/XSLT, uPortal ASP.NET/VB.NET, DotNetNuke, BREW, akarta Strust Framework, Jakarta Velocity, Web-based Application: ASP.NET/C#/VB.NET/.NET Technologies, INetStrust Framework, MS SQL 2000
Oracle
PostgreSQL
Bid Time: 06-11-2008 03:20
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San Jose,
US
location |
US$3,000
bid amount |

(No Feedback
Yet)
feedback |

20 day(s)
delivery time |

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What's your project location requirement? So I can discuss the project more in detail.
Regards,
Jenny Barry
Bid Time: 06-08-2008 21:31
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GUANGZHOU,
CN
location |
US$3,000
bid amount |

(No Feedback
Yet)
feedback |

19 day(s)
delivery time |

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We can do you project. Please, check your PM. Thanks
We are skilled in C++©JAVA©vb.net©asp.net Application development for 5-10 years. So We can do you project.
Bid Time: 06-08-2008 19:54
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bangalore,
IN
location |
US$5,500
bid amount |

(No Feedback
Yet)
feedback |

90 day(s)
delivery time |

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Hi Shlomoh,
I am interested in doing your project. I have experience in SAS/SATA design verification reputed organizations.
Thanks & Regards,
Sree
Bid Time: 06-10-2008 11:05
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Jerusalem,
IL
location |
US$3,600
bid amount |

(No Feedback
Yet)
feedback |

120 day(s)
delivery time |

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The Project Will be Implemented on an FPGA. The Code will be written in VHDL
the system will be a PSOC ( Programmable system on a chip)
It Will Inlude a 16 Bit CPU+ RAM & ROm Etc, , A SCSI Core and a sata core.
The one chip code will be designed in ASM or C as your preference.
The design schedule assuming 1/jul/08 start point will be :
30/July/2008 - Spec Completion + Core Buy.
30/Aug/08 - CPU + Core Integration + VHDL Simulation
30/Sep/08 - ASM/C Code Writing + System Simulation
30/Oct/08 - Synthesis to FPGA + Integration On FPGA Demo Board
The Deliverable for the FPGA System will be:
1.0 - Detailed FPGA Spec.
2.0 - FPGA VHDL Code listing.
3.0 - On Chip CPU ASM Code Listing.
4.0 - 50 Basic & Detailed & System Simulation Test Benches.
5.0 - Synthesized System on An FPGA Demo Board.
The Task Price will be - 3,600 $
Bid Time: 06-25-2008 02:08
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